Employing a High-Level Language for Porting Numerical Applications to Reconfigurable Hardware
AbstractThe deployment of FPGAs has become more and more common over the last years. Many applications have since then been accelerated by porting advantageous parts onto FPGA hardware. High-level, C-like programming languages and advanced tools such as Impulse CoDeveloper that produce hardware descriptions can potentially help with this task. We showcase the applicability of this new approach to FPGA acceleration in terms of solving the Poisson equation with the conjugate gradient (CG) method and a red-black symmetric successive over-relaxation (SSOR) preconditioner as a model problem. In this case, the CPU executes the CG method while an FPGA takes over the red-black SSOR preconditioning part. We compare a purely CPU-based algorithm to our FPGA-extended approach in order to evaluate the maturity and applicability of high-level language translators with regard to accelerating numerical applications.
The Engineering Mathematics and Computing Lab (EMCL), directed by Prof. Dr. Vincent Heuveline, is a research group at the Interdisciplinary Center for Scientific Computing (IWR).
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